A metal-insulator (oxide) semiconductor field effect transistor (MISFET or MOSFET) is a basic element of a semiconductor device. The MISFET is miniaturized more and more as miniaturization and high integration of the semiconductor device progress.
A structure in which an n-channel MISFET (hereinafter also referred to as NTr) and a p-channel MISFET (hereinafter also referred to as PTr) are included on the same substrate is generally called a CMOS circuit.
The CMOS circuit is widely used as a device included in many kinds of LSIs because power consumption is low as well as miniaturization and high integration are easy to realize high-speed operation in the device.
In related art, as a gate insulating film, a thermally-oxidized film of silicon (silicon oxide: SiO2) or a film formed by nitriding the silicon oxide thermally or in plasma (silicon oxynitride: SiON) is widely used.
As a gate electrode, an n-type polysilicon layer to which phosphorus (P) or arsenic (As) is doped and a p-type polysilicon layer to which boron (B) is doped have been widely used to the NTr and the PTr.
However, when the gate insulting film is allowed to be thinner or a gate length is allowed to be reduced in accordance with a scaling law, increase of gate leak current and reduction of reliability occur by allowing the silicon oxide film and the silicon oxynitride film to be thinner.
Additionally, reduction of gate capacitance occurs due to a depletion layer formed in the gate electrode, therefore, a method of using an insulating material having a high-dielectric constant (a high-dielectric film) is used as the gate insulating film and a method of using a metal material as the gate electrode are proposed.
As materials for the high-dielectric film, for example, hafnium compounds and so on can be cited. Particularly, hafnium oxide (HfO2) is a promising material in a point that reduction in electron/hole mobility can be suppressed while maintaining a high dielectric constant.
However, as disclosed in “High Performance nMOSFET with Hfsix/Hf02 Gate Stack by Low Temperature Process”, T, Hirano et al., Tech. Dig. IEDM, p. 911 (2005) (Non-Patent Document 1), there is a problem that the reduction in characteristics such as reduction in carrier mobility occurs by performing high-temperature processing such as an activation annealing process of source/drain (S/D).
As metal materials for making a gate electrode, materials having a desired value in the work function (WF) can give good transistor characteristics.
In order to increase performance of an LSI, it is necessary that a short channel effect and so on are suppressed while achieving a lower threshold value as the MISFET, and metal materials of the gate electrode are desired to have the WF close to 4.1 eV in the NTr and 5.2 eV in the PTr.
Not so much metal material satisfying the above is known, and there is description of hafnium silicide (HfSix) in the NTr, ruthenium (Ru) and titanium nitride (TiN) in the PTr in “High Performance nMOSFET with HfSix/Hf02 Gate Stack by Low Temperature Process”, K. Tai et al., ISTC, p 330 (2006); “High Performance Dual Metal Gate CMOS with High Mobility and Low Threshold Voltage Applicable to Bulk CMOS Technology”, S. Yamaguchi et al., Symp. VLSI Tech., p. 192 (2006); “Sub-1 nm EOT HfSix/Hf02 Gate Stack Using Novel Si Extrusion Process for High Performance Application”, T. Ando et al., Symp. VLSI Tech., p. 208 (2006); and “High Performance pMOSFET with ALD-TiN/Hf02 Gate Stack on (110) Substrate by Low Temperature Process”, K. Tai et al., ESSDERC., p. 121 (2006) (Non-Patent Documents 2 to 5) and the like.
However, the WF value varies also in the above materials by performing a high-temperature processing step, which generates reduction of characteristics such as reduction in carrier mobility.
Accordingly, a manufacturing method in which a gate insulating film and a gate electrode are formed after performing the high-temperature processing step is disclosed in JP-A-2000-40826 (Patent Document 1) with respect to a related art manufacturing method in which the high-temperature processing step is performed after forming the gate insulating film and the gate electrode.
Hereinafter, a transistor structure formed by the manufacturing method in which the gate insulating film and the gate electrode are formed after performing high-temperature processing step will be referred to as a “gate-last structure”.
On the other hand, a transistor structure formed by performing the high-temperature processing step after forming the gate insulating film and the gate electrode as in the related art will be referred to as a “gate-first structure”.
In JP-A-2002-198441 (Patent Document 2), a method of forming the gate electrode by using metals having suitable WF on the NTr and the PTr respectively in the gate-last structure is disclosed.
In this case, a dummy gate is removed in a first region, a first gate insulating film is formed, a first gate electrode is formed by using a metal and the metal other than the portion to be the first gate electrode is removed by etching.
Next, a dummy gate is removed in a second region, a second gate insulating film is formed, a second gate electrode is formed and metal other than the portion of the second gate electrode is removed by etching.
According to the above processes, the gate electrodes having suitable WF can be formed on the NTr and the PTr respectively.
As the example applying the gate-last structure, a Full Silicidation (FUSI) technique using a compound of a polysilicon layer and a transition metal applying the metal as the gate electrode as described above.
It is difficult to form the NTr and the PTr by optimizing silicidation respectively, however, a method of fully siliciding only the gate electrode of the PTr by making an opening only in a PTr region as in JP-A-2009-117621 (Patent Document 3) is known.
In recent years, a technique (hereinafter, referred to as e-SiGe structure) of forming silicon germanium (SiGe) having a different lattice constant from silicon on a source/drain of transistors is known.
Moreover, a technique of modulating stress in a channel region of the transistor by forming a silicon nitride film (hereinafter, referred to as a stress liner film SL) of tensile stress or compression stress on the source/drain to thereby improve carrier mobility is applied as in International Publication WO2002/043151 pamphlet (Patent Document 4).
In the case where the stress liner film is formed on the source/drain in the transistor having the gate-last structure, a structure and a forming method in which an upper portion of the stress liner film is polished by a chemical mechanical polishing process and removed are applied such as in JP-A-2008-263168 (Patent Document 5).
Accordingly, the stress in the channel direction is reinforced to thereby realize a high-performance transistor having high carrier mobility.
In the above structure in which the upper portion of the stress liner film of the gate-last structure is polished by the CMP process and removed, the action of the stress due to the stress liner film is changed when removing the polysilicon layer which is a dummy gate. A difference occurs in effects with respect to carrier mobility between the NTr and the PTr due to the above change as shown in the following expressions (1), (2).
                                          μ            xx                                μ            0                          =                  1          +                      0.316            ⁢                                                  ⁢                          S              xx                                -                      0.534            ⁢                                                  ⁢                          S              yy                                +                      0.176            ⁢                                                  ⁢                          S              zz                                                          (        1        )                                                      μ            xx                                μ            0                          =                  1          -                      0.718            ⁢                                                  ⁢                          S              xx                                +                      0.011            ⁢                                                  ⁢                          S              yy                                +                      0.663            ⁢                                                  ⁢                          S              zz                                                          (        2        )            
The expression (1) indicates an effect of a stress (Sxx, Syy, Szz) with respect to a ratio of mobility of electrons (μxx/μ0). The expression (2) indicates an effect of the stress (Sxx, Syy, Szz) with respect to the ratio of mobility of holes (μxx/μ0). Here, “xx” denotes a channel-length direction, “yy” denotes a vertical direction with respect to the channel and “zz” denotes a channel-width direction.
In Patent Document 5, the stress liner film of tensile stress is provided in the NTr and the stress liner film of compression stress is applied to the PTr.
In the case of the NTr in which electrons are carriers, the tensile stress in the “xx” direction (+Sxx) is increased and the compression stress in the “yy” direction (−Syy) is reduced, thereby cancelling effects to the mobility as a coefficient of Sxx is approximately the same as a coefficient of Syy.
On the other hand, in the case of the PTr in which holes are carriers, the compression stress in the “xx” direction (+Sxx) is increased and the tensile stress in the “yy” direction (−Syy) is reduced, however, the coefficient of Sxx is larger than the coefficient of Syy by approximately 70 times, thereby obtaining effects of the increase of mobility due to action in the “xx” direction.
FIG. 10 shows results obtained by plotting relative variations of mobility in respective processes with respect to the gate pitch in the NTr having the gate-last structure. In the drawing, (a) indicates mobility after forming the stress liner, (b) indicates mobility after removing the stress liner on the gate electrode, (c) indicates mobility after removing the polysilicon and (d) indicates mobility after forming the metal gate electrode. The relative mobility when there is no stress liner film is set to 1.0.
When the gate pitch is long (0.83 μl, 0.5 μm), the mobility is relatively increased after removing the polysilicon layer as shown in (c), whereas when the gate pitch is short (0.19 μm), the mobility is relatively reduced after removing the polysilicon layer.
This is because the effects to the mobility are cancelled as the coefficient of Sxx is the approximately same as the coefficient of Syy, as described above and that Sxx is relatively reduced when the gate pitch is short, as a result, the mobility is reduced.
Accordingly, it is found that, as the distance between gates is reduced due to miniaturization of the semiconductor device, characteristics of the NTr is reduced in the gate-last structure is reduced as compared with the gate-first structure.
In the structure of Patent Document 3, a technique for applying the gate-first structure only to the NTr is disclosed.
However, as the process of removing the polysilicon layer in the PTr in the structure of Patent Document 3, the mobility of the PTr is not increased though reduction of mobility of the NTr is suppressed, therefore, it is difficult to obtain the high-performance CMOS circuit.
Additionally, there is a description concerning a method of using a high-dielectric constant film as the gate insulating film and using a metal material as the gate electrode in, for example, “A Novel “Hybrid” High-k/Metal Gate Process for 28 nm High Performance CMOSFETs”, C. M. Lai et al., Tech. Dig. IEDM, p. 655 (2009) (Non-Patent Document 6).
The CMOS structure disclosed in Non-Patent Document 6 applies the gate-first structure for the NTr and applies the gate-last structure for the PTr, however, the CMOS structure has a process of removing the upper portion of the stress liner film by the chemical mechanical polishing process and removing the polysilicon layer in the NTr. Accordingly, the reduction of mobility in the NTr occurs. As a result, it is difficult to obtain the high-performance CMOS circuit particularly in a micro area in which the distance between gates is short.